1. Field of the Invention
The present invention relates to a phase-locked loop of a video display device, and more particularly, to a phase-locked loop capable of dynamically adjusting a phase of an output signal according to a detection result of a phase/frequency detector, and a method thereof.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a pixel sequence corresponding to a pixel driving clock CLK0 while a horizontal synchronization signal HS0 in a prior art video display device (not shown) has a phase shift. A phase-locked loop of the video display device generates the pixel driving clock CLK0 according to the horizontal synchronization signal HS0. H1, H2, H3, etc, which are shown in FIG. 1, respectively represent initial periods corresponding to a first row of pixels, a second row of pixels, a third row of pixels, etc. in the pixel driving clock CLK0, and timing of the driving periods (A2,1), (A2,2), (A2,3), etc. relative to the initial period H2 in the second row of pixels equals timing of the driving periods (A1,1), (A1,2), (A1,3), etc. relative to the initial period H1 in the first row of pixels. If an average period of the horizontal synchronization signal HS0 is T, and the phase-locked loop locks a frequency corresponding to the average period T, the above-mentioned initial periods H1, H2, H3, etc. align initial positions of the driving periods of respective rows of pixels, as shown in FIG. 1. When the horizontal synchronization signal HS0 in the initial position of the driving periods of the second row of pixels has a phase shift corresponding to time difference ΔT, the second row of pixels shown by the video display device may have errors.
For example, if frequency of the horizontal synchronization signal HS0 is 60 kHz and frequency of the pixel driving clock CLK0 is 80 MHz, a period T of the horizontal synchronization signal HS0 may be ten or more microseconds, a horizontal scanning period corresponding to a pixel may be ten or more nanoseconds, and the above-mentioned time difference ΔT may be several nanoseconds. Because response time of the phase-locked loop is usually greater than the time difference ΔT, the phase-locked loop is unable to adjust the pixel driving clock instantaneously, merely letting the above-mentioned phase shift occur repeatedly. As a result, other rows of pixels displayed by the video display device may have errors due to phase shifts.